Verilog Cheat Sheet
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2Verilog Cheat Sheet
S Winberg and J Taylor
Comments
Operators
// One-liner
// These are in order of precedence...
/* Multiple
// Select
lines */
A[N] A[N:M]
// Reduction
&A ~&A |A ~|A ^A ~^A
Numeric Constants
// Compliment
// The 8-bit decimal number 106:
!A ~A
8'b_0110_1010
// Binary
// Unary
8'o_152
// Octal
+A -A
8'd_106
// Decimal
// Concatenate
8'h_6A
// Hexadecimal
{A, ..., B}
"j"
// ASCII
// Replicate
{N{A}}
78'bZ
// 78-bit high-impedance
// Arithmetic
A*B A/B A%B
A+B A-B
Too short constants are padded with zeros
// Shift
on the left.
Too long constants are
A<<B A>>B
truncated from the left.
// Relational
A>B A<B A>=B A<=B
Nets and Variables
A==B A!=B
wire
[3:0]w;
// Assign outside always blocks
// Bit-wise
reg
[1:7]r;
// Assign inside always blocks
A&B
reg
[7:0]mem[31:0];
A^B A~^B
A|B
integer
j;
// Compile-time variable
// Logical
genvar
k;
// Generate variable
A&&B
A||B
// Conditional
Parameters
A ? B : C
parameter
N
= 8;
localparam
State = 2'd3;
Module
module
MyModule
Assignments
#(parameter
N = 8)
// Optional parameter
assign
Output = A * B;
(input
Reset, Clk,
assign
{C, D} = {D[5:2], C[1:9], E};
output
[N-1:0]Output);
// Module implementation
endmodule
Module Instantiation
// Override default parameter: setting N = 13
MyModule #(13) MyModule1(Reset, Clk, Result);
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